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ADM1041
Table 36. Register 1Bh, Sel CBD/SMBAlert2. Power-On Default from EEPROM Register 811Bh during Power-Up.
Bit No.
7
6
5
4
3
2
1
0
Name
selcbd2 <7>
selcbd2 <6>
selcbd2 <5>
selcbd2 <4>
selcbd2 <3>
selcbd2 <2>
selcbd2 <1>
selcbd2 <0>
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
V DD OK b (inverted)
mfg1
mfg2
mfg3
mfg4
m_cbd_w Microprocessor Control of CBD
mfg5
Not used.
Table 37. Register 1Ch, Manufacturer’s ID. Power-On Default 41h.
Bit No.
7–0
Name
Manufacturer’s ID
Code
R/W
R
Description
This register contains the manufacturer’s ID code for the device. It is used by the manufacturer
for test purposes and should not be read from or written to in normal operation.
Table 38. Register 1Dh, Revision Registe r. Power-On Default 01h.
Bit No.
7–4
3–0
Name
Major Revision Code
Minor Revision Code
R/W
R
R
Description
These 4 bits denote the generation of the device.
These 4 bits contain the manufacturer’s code for minor revisions to the device. Rev 0 = 0h, Rev
1 = 1h, and so on.
This register is used by the manufacturer for test purposes. It should not be read from or
written to in normal operation.
Table 39. Register 2Ah, Status1 Mirror. Power-On Default 00h.
These flags are cleared by a register read, provided the fault no longer persists.
Bit No.
7
6
5
4
3
2
1
0
Name
ovfault_L
uvfault_L
ocpto_L
mfg1_L
mfg2_L
mfg3_L
mfg4_L
mfg5_L
R/W
R
R
R
R
R
R
R
R
Description
Overvoltage fault has occurred.
Undervoltage fault has occurred.
Overcurrent has occured and timed out (ocpf is in Status3).
MON1 flag.
MON2 flag.
MON3 flag.
MON4 flag.
MON5 flag.
Note that latched bits are clocked on a low-to-high transmission only. Also note that these
register bits are cleared when read via the SMBus, except if the fault is still present. It is
recommended to read the register again after the faults disappear to ensure reset.
Rev. A | Page 50 of 64
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